timing·WaveDrom signal notation·hardware, embedded·complexity 2/3·since v0.1.0

I2C read burst timing

WaveDrom-compatible timing diagram for an I2C register read with address, repeated start, data bytes, ACK, and NACK phases.

For the firmware engineer

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timing·§ WaveJSON

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UTF-8 · LF · 10 lines · 242 chars✓ parsed·2.4 ms·7.0 KB SVG

Scenario

I2C reads are visually clearer as timing diagrams than as prose. The repeated start and ACK/NACK phases are where firmware and hardware teams most often talk past each other.

Annotation key

[Control], [Bus], and [Status] group related signals.
p renders clock pulses.
= segments carry bus labels from the data: list.

Timing syntax →