SPI modes 0–3: CPOL, CPHA, and a 2 MHz timing check

In the conventional SPI mode numbering used by Linux, CPOL sets SCLK's inactive level and CPHA selects the capture edge: CPHA=0 captures on the leading edge, while CPHA=1 captures on the trailing edge. Because CPOL=0 starts low and CPOL=1 starts high, the four combinations map to Modes 0–3. For the worked Mode 0 transfer below, sending one 8-bit word at 2 MHz takes 8 / 2 MHz = 4.0 µs of active clock time, and the receiver captures 0xA6 as 1 0 1 0 0 1 1 0 on eight rising edges.

Scope and terms before choosing a mode

SPI is a family of synchronous serial interfaces, not one formal industry standard. Texas Instruments says the configurable SPI in its SPRUGP2A guide does not conform to a specific industry standard, and the Linux kernel documentation likewise warns that vendors implement the protocol in slightly different ways. A mode table is therefore a translation aid—not a substitute for the controller manual, target datasheet, and their timing diagrams.

This note uses four common signals:

The leading edge is the first SCLK transition away from idle after selection. The trailing edge is the return transition. CPOL (clock polarity) determines which physical transition is leading. CPHA (clock phase) determines whether capture occurs on that leading transition or the following trailing transition. "Capture" means the receiver samples the line; "launch" or "change" refers to the opposite edge commonly used to present the next bit.

Bit order is separate from clock mode. The TI guide, for example, configures MSB-first versus LSB-first independently of its polarity and phase fields. Selecting Mode 0 does not by itself say whether 0xA6 leaves as 10100110 or 01100101.

Translate CPOL and CPHA into the four modes

The Linux convention treats CPOL as the high-order mode bit and CPHA as the low-order bit. That gives this crosswalk:

Two checks make this table easier to reconstruct than memorize. First, changing CPOL flips the idle level and therefore flips which physical edge is leading. Second, changing CPHA leaves the idle level alone but moves capture from the leading edge to the trailing edge.

Do not assume a vendor's field named PHASE, CKE, or a similar term has the same numeric sense as CPHA. TI SPRUGP2A's table describes its own POLARITY and PHASE bits in terms of when data is output and latched. The safe workflow is to reduce both manuals to four observable facts: idle level, first edge, capture edge, and bit order. Compare those facts, not just enum names.

Worked Mode 0 transfer: 0xA6 at 2 MHz

The fictional link uses these explicit inputs and assumptions:

Convert the hexadecimal byte before reading the waveform:

0xA6 = 0b1010_0110

D7 D6 D5 D4 D3 D2 D1 D0
 1  0  1  0  0  1  1  0

At 2 MHz, one clock period is:

T_SCLK = 1 / f_SCLK
       = 1 / (2 × 10^6 s^-1)
       = 0.5 × 10^-6 s
       = 0.5 µs.

Each ideal half-cycle is 0.25 µs. Eight complete periods require:

t_clock = 8 bits × 0.5 µs/bit
        = 4.0 µs.

That 4.0 µs is only the active clock interval. The full assertion time of nCS can be longer because a real target may require time from nCS falling to the first clock edge and from the last clock edge to nCS rising. Those limits must come from the target datasheet and must be checked against the host's actual timing—not inferred from this ideal diagram.

For Mode 0, SCLK is low before nCS becomes active. Because CPHA=0, D7 must already be valid before the first rising edge. The receiver then captures one bit on each rising edge in this order:

Reading those samples from first to last reconstructs 10100110₂ = 166₁₀ = 0xA6.

Reproducible Schematex source

timing "SPI Mode 0: 0xA6, MSB first" [hscale: 2]
nCS:     10000000001
SCLK:    00pppppppp0
MOSI:    x110100110x
Capture: xx========x  data: ["↑D7","↑D6","↑D5","↑D4","↑D3","↑D2","↑D1","↑D0"]

Schematex 1.0.13 strictly parsed and rendered this source with no diagnostics on August 31, 2026. All four rows have eleven aligned cells: one idle cell, one illustrative pre-clock setup cell after nCS falls, eight data periods, and one post-transfer cell. D7 is repeated across the setup and first-clock cells so it is visibly established before the first rising edge. The current timing syntax reference defines p as one positive clock period, x as unknown or outside the defined transfer, and = as a labeled bus segment.

The capture row is explanatory, not an extra wire. Current Schematex timing syntax does not implement fractional phase offsets or edge-to-edge annotation arrows, so the figure identifies capture order but does not claim a numerical setup or hold interval. That boundary is deliberate: a logical waveform can expose mode and bit-order mistakes, while an electrical timing sign-off needs the real controller and target limits.

Checks and invariants

Use these checks before trusting a configuration or a logic-analyzer decode:

1. CPOL=0 means SCLK is low while inactive; the diagram begins and ends low.
2. CPHA=0 means capture occurs on the leading edge; with CPOL=0, all eight capture edges are rising.
3. There are exactly eight SCLK periods, eight capture labels, and eight transmitted bits.
4. 0xA6 expands to 10100110 MSB first. Reversing the order yields 01100101, or 0x65, which is a different transfer.
5. 2 MHz × 4.0 µs = 8 clocks. Units cancel to a dimensionless clock count.
6. Data changes do not occur at the stated capture edge in the ideal model; each captured value is stable across its rising edge.
7. nCS remains asserted for the complete eight-clock transaction.
8. Changing only CPOL from 0 to 1 must change the idle and leading-edge polarity; changing only CPHA must move capture between leading and trailing edges.

Failure modes and review boundary

Correct mode, wrong bit order. A decoder can show clean edges but return 0x65 instead of 0xA6 when one endpoint is LSB first.

Correct labels, wrong electrical margin. The logic may match Mode 0 while setup time, hold time, clock high/low time, rise time, or chip-select timing violates a datasheet limit. This figure supplies none of those limits.

Mode changed after selection. The Linux documentation notes that clock mode matters as soon as chip select becomes active. Configure the idle level before asserting nCS; do not let selection expose a spurious first edge.

Assuming all SPI devices share one convention. SPI has no single formal specification. Some devices support only selected modes, use one bidirectional data line, require command/address/dummy phases, or assign different names to the same timing behavior.

Treating a captured trace as system approval. One correct byte does not establish signal integrity, worst-case timing, voltage compatibility, reset behavior, concurrency safety, or suitability for a safety-related function.

Reproduce the trace, then challenge it

Paste the source into the Schematex playground. First change the eight p cells in SCLK to n: the clock now begins each active cell high-to-low and no longer represents the stated Mode 0 polarity. Then reverse the eight data bits to 01100101 while retaining the idle, setup, and post-transfer cells; the capture order should decode 0x65, proving that clock mode and bit order are independent configuration choices. Before applying either result to hardware, replace the fictional frequency and timing assumptions with the two device manuals and the measured trace.