Circuit schematic

About circuit schematics

A circuit schematic is the standard graphical representation of an electronic circuit — components drawn as standardized symbols, connected by wires, with enough information to build or simulate the circuit. Electronics engineers use them throughout the product lifecycle: from initial concept to PCB layout review and datasheet documentation. Schematex follows IEEE Std 315-1975 / ANSI Y32.2 and IEC 60617 for component symbols.

The DSL has two modes. Netlist mode (recommended) is SPICE-style: you list components and the nodes they connect to, and the engine lays everything out automatically — each line is self-contained, with no spatial state to track. Positional mode is for hand-drawing: components chain in a direction like Schemdraw. Both produce the same SVG. For generated diagrams (e.g. by an LLM), always use netlist mode — it has by far the smaller error surface.

1. A minimal circuit (netlist mode — recommended)

The smallest useful circuit: a voltage source, a resistor, and a capacitor to ground — an RC low-pass filter.

Three rules cover ~90% of netlist usage:

1. Start with circuit "Title" netlist (the netlist keyword switches on this mode).
2. Each line is componentId nodeA nodeB value — one component, the two (or more) named nodes it connects to, then its value.
3. Two components that share a node name are wired together. 0, gnd, or GND is the ground net (a ground symbol is drawn automatically).

The component-id prefix sets the symbol: R*→resistor, C*→capacitor, L*→inductor, V*→voltage source, D*→diode, Q*→BJT. When the prefix is ambiguous, add type= (e.g. X1 a b type=opamp). You never compute coordinates — the engine derives placement from the connectivity.

Comments must start with # on their own line.

2. Components

2.1 Netlist mode syntax

A netlist line has the form:

componentId node... [value] [type=…] [label="…"]

The positional nodes come first; a trailing token that doesn't look like a node becomes the value. Example — a transistor (4 nodes) and a resistor:

Q1 c b e npn        # collector, base, emitter nodes + model
Rc vcc c 2.2k       # two nodes + value

Optional orientation hint. The engine auto-orients symbols by role (sources up, ground down, the rest horizontal). To nudge a single symbol, add dir=right|left|up|down — connectivity is unchanged, only the symbol's facing rotates:

C1 out 0 100n dir=down    # draw C1 as a shunt cap hanging to ground

This is the lightweight layout-control layer (like Lcapy's per-component orientation): netlist connectivity does the heavy lifting, dir= only refines appearance. For full geometric control, use positional mode below.

2.2 Positional mode syntax (hand-drawing)

Positional mode is for manually laying out a schematic geometrically. Prefer netlist mode for generated output — positional mode requires tracking a moving "cursor" across lines, which is error-prone for LLMs.

A named component line has the form:

id: type direction [value="…"] [label="…"]

An anonymous component omits the id: prefix — the parser assigns an auto ID.

R1: resistor right value="4.7k" label="R1"
capacitor down value="100n"

Direction is one of right (default), left, up, down. It controls which way the component extends from the current cursor position.

2.3 Passive components

2.4 Sources and power

2.5 Semiconductors — diodes

2.6 Semiconductors — transistors

2.7 Analog ICs and op-amps

2.8 Switches and relays

2.9 Electromechanical and measurement

2.10 Connectors and annotations

3. Wiring and branching

3.1 Wire segments

wire direction [N] draws a bare wire from the current cursor in the given direction. An optional number sets the length in pixels.

wire right
wire down 40
wire left 20

3.2 Jumping the cursor with at:

at: id.end moves the cursor to a named anchor without drawing anything. Use it to branch from a previously placed component.

R1: resistor right value="10k"
at: R1.end
C1: capacitor down value="100n"

Named anchor suffixes: end, start. Components retain their ID across the whole diagram, so you can jump back to any previously placed component.

3.3 Junction dots

Place a dot (or use net NAME: dot) to mark a T-junction — a point where three or more wires meet. Without a dot, crossed wires are drawn as a crossover (no connection).

R1: resistor right
dot
wire right           # continues from R1.end
at: R1.end
C1: capacitor down   # branches down from the same point

3.4 Named nets

net NAME declares a named net. net NAME: dot declares the net and places a junction dot at the current cursor, remembering that location. Later, at: NAME jumps back to that net's anchor.

net VOUT: dot
R2: resistor right value="10k"
at: VOUT
C1: capacitor down value="470n"

3.5 Net labels

label "text" direction? places a text label at the current cursor position. Labels do not advance the cursor. They are useful for naming power rails or inter-sheet connections.

label "VCC" up
label "GND" down

4. Netlist mode

Add netlist after the title on the header line to switch to SPICE-style netlist parsing. The auto-layout engine computes component positions from the net connectivity.

circuit "Low-pass filter" netlist

4.1 Netlist line format

Each line is: ID net1 net2 [net3…] [value] [key=value…]

• ID — component identifier. The first letter determines the default type (SPICE prefix convention).
• net1, net2, … — net names the pins connect to. Net names matching 0, gnd, ground, earth, pe, agnd, dgnd, gnda, gndd, vss, or com (case-insensitive, with optional _<word> or numeric suffix — e.g. gnd_ref, AGND_DIG, EARTH1) all canonicalize to the ground net.
• value (optional bare token) — component value or model name.
• key=value (optional) — label=, value=, type= overrides.

4.2 SPICE prefix → component type

Scope: schematex circuit covers electrical schematics only (IEEE 315 / IEC 60617). Hydraulic and pneumatic schematics (ISO 1219) use a fundamentally different visual grammar — directional valve envelopes, cylinder symbols, line styles for pressure/return/drain — and are not supported by this engine. Hydraulic prefixes such as EV* (electrovalve), BOMBA* (pump), TANK*, DIPOSIT* will be rejected with a "cannot infer type" error.

4.3 Transistor model override

For Q lines, a trailing model name overrides the type:

Q1 c b e npn      # NPN BJT
Q2 c b e pnp      # PNP BJT
M1 d g s nmos     # N-channel MOSFET
M2 d g s pmos     # P-channel MOSFET

For D lines, similarly:

D1 anode cathode zener
D2 anode cathode led
D3 anode cathode schottky
D4 anode cathode photodiode

4.4 Netlist example

5. Attributes

Both positional and netlist modes accept these key=value attributes:

In positional mode, at= inside the component line is equivalent to a preceding at: line:

C1: capacitor down at=R1.end value="100n"

6. Labels & comments

• Diagram title: circuit "RC Filter" — first line only.
• Component label: label="R1" attribute — reference designator shown beside the symbol.
• Value annotation: value="4.7k" — shown beside or below the component.
• Net label: label "VOUT" right — standalone net flag at the current cursor.
• Comments: # at the start of a line (after leading whitespace).

7. Reserved words & escaping

Reserved at line start (positional): circuit (header), at:, net, wire, label.

Reserved in netlist mode: same header rules apply; all other lines are SPICE component lines.

Ground net aliases (netlist only): 0, gnd, GND, Gnd, ground, Ground — all treated as the same node.

Component IDs must match [a-zA-Z_][a-zA-Z0-9_]*. Spaces in values must be quoted: value="10 kΩ".

8. Common mistakes

9. Grammar (EBNF)

document        = header statement*

-- Positional mode --
header          = "circuit" ( WS quoted-string )? NEWLINE
statement       = blank | comment | component | wire | at | net-decl | label-stmt

component       = ( id ":" WS )? type WS direction? attrs* NEWLINE
wire            = "wire" ( WS direction )? ( WS integer )? NEWLINE
at              = "at:" WS anchor NEWLINE
anchor          = id "." ( "start" | "end" )
                | id                          // net name anchor

net-decl        = "net" WS id NEWLINE         // declare net only
                | "net" WS id ":" WS "dot" NEWLINE  // declare + place dot

label-stmt      = "label" WS quoted-string ( WS direction )? NEWLINE

component-attr  = "value=" quoted-string
                | "label=" quoted-string
                | "at=" anchor
                | "length=" integer

direction       = "right" | "left" | "up" | "down"
type            = // any value from §2 component tables

-- Netlist mode --
netlist-header  = "circuit" ( WS quoted-string )? WS "netlist" NEWLINE
netlist-stmt    = id WS net-ref+ ( WS kv-pair )* NEWLINE
                | comment
net-ref         = id | "0"                    // net name or ground alias
kv-pair         = id "=" ( quoted-string | bare-value )

id              = [a-zA-Z_] [a-zA-Z0-9_]*
integer         = [0-9]+
quoted-string   = '"' any-char-but-quote* '"'
comment         = "#" any NEWLINE

Authoritative source: src/diagrams/circuit/parser.ts and src/diagrams/circuit/netlist.ts. If this diverges from the parser, the parser wins — please open an issue.

10. Standard compliance

Schematex circuit schematics follow IEEE Std 315-1975 / ANSI Y32.2 for component symbol shapes and IEC 60617 for international variants. The netlist syntax follows SPICE prefix conventions (Berkeley SPICE3 / LTspice / ngspice).

What is implemented today:

• ✅ Full passive component set: resistor variants, capacitor variants, inductor variants, crystal, transformer
• ✅ Sources and power: voltage source, current source, AC source, battery, VCC, four ground styles
• ✅ Diode family: diode, zener, schottky, LED, photodiode, varactor, TVS, bridge rectifier
• ✅ BJTs: NPN, PNP, Darlington NPN/PNP
• ✅ FETs: NMOS/PMOS enhancement, NMOS depletion, N/P-channel JFET
• ✅ Power semiconductors: IGBT, SCR, TRIAC, DIAC
• ✅ Optoelectronics: phototransistor, optocoupler
• ✅ Analog ICs: op-amp, comparator, Schmitt buffer, tri-state buffer, INA, generic IC, voltage regulator, DC-DC converter, 555 timer
• ✅ Switches: SPST, SPDT, DPDT, push-NO, push-NC
• ✅ Relays: coil, NO contact, NC contact
• ✅ Electromechanical: motor, speaker, microphone, buzzer
• ✅ Measurement: ammeter, voltmeter, wattmeter, oscilloscope
• ✅ Annotations: wire, dot, label, port, test point, no-connect, antenna
• ✅ Positional DSL: direction chaining, at: branching, net declarations
• ✅ Netlist DSL: SPICE prefix mapping, model overrides, auto-ground synthesis
• ⏳ Pin-level at: for BJT/FET/op-amp named pins (base, collector, plus, minus, out)
• ⏳ Auto-routed wires in positional mode (routing around placed symbols)
• ⏳ Bus wires with bit-width annotation (/8 slash)

References:

• IEEE Std 315-1975 (ANSI Y32.2): Graphic Symbols for Electrical and Electronics Diagrams
• IEC 60617: Graphical symbols for diagrams
• SPICE3 User's Manual, UC Berkeley — netlist line format conventions

11. Related examples

12. Roadmap

Planned — not yet parseable. Do not use these in generated DSL today; the parser will reject or ignore them.

• Named pin anchors for multi-pin components — at: Q1.base, at: U1.out, at: U1.plus so op-amp and BJT feedback loops can be wired without long wire detours.
• Bus wire — wire right bus=8 drawing a thick wire with a /8 bit-width slash annotation.
• Auto-routed wires — connect R1.end U1.minus letting the engine route the wire around placed symbols.
• flip and reverse attributes — mirror or reverse a component's polarity/orientation along the direction axis.
• dashed wire style — dashed line for RF shields, cable bundles, or virtual connections.
• Hierarchical sheets — module "name" { … } grouping analogous to logic gate modules, for documenting multi-sheet schematics.

Track in the GitHub issues if you need any of these sooner.