Logic gate diagram

About logic gate diagrams

A logic gate diagram shows how Boolean functions are implemented in hardware — inputs flow left through combinational gates and flip-flops to produce outputs on the right. Digital design engineers use them to document RTL intent, verify gate-level netlists, and teach Boolean algebra. Schematex derives its symbol set from IEEE Std 91-1984 / ANSI Y32.14 (distinctive-shape ANSI symbols, the US default) and IEC 60617-12 (uniform rectangle symbols, the international default), selectable per diagram.

The DSL is functional: you declare signals and describe each gate's inputs by name. Layout and wiring are computed automatically from the dependency graph — no manual coordinates.

1. Your first logic gate diagram

The smallest useful diagram: two inputs, one gate, one output.

Four rules cover 80% of usage:

1. Start with the keyword logic, optionally followed by a quoted title and style: ansi or style: iec.
2. Declare ports with input and output lines — comma-separated signal names.
3. Each gate is id = GATE_TYPE(input1, input2, …). The id becomes a named signal wire.
4. An output name that matches a gate id is automatically wired; use OUTPUT <- gate_id when the names differ.

Comments must start with # or -- on their own line (or after the last token on a gate line).

2. Gate types

2.1 Combinational gates

2.2 Special-output buffers

2.3 Flip-flops and latches

2.4 Complex combinational

2.5 Sequential complex

3. Inputs and outputs

3.1 Declaring ports

input A, B, Cin          # three input ports
output Sum, Cout         # two output ports

Each name in an input or output list becomes a named signal wire available throughout the diagram.

3.2 Active-low inputs

Prefix a signal name with ~ in the input list to mark it as active-low. The renderer draws a bubble at the port symbol.

input ~nRESET, CLK, DATA

Active-low notation also works inside gate input lists:

g1 = AND(~nRESET, CLK)

3.3 Wiring outputs to gates

If the output ID matches a gate ID, the connection is implicit:

output Sum        # Sum is also a gate id → auto-wired
Sum = XOR(s1, Cin)

When the names differ, use the explicit assignment operator:

output F
q1 = NOR(A, B)
F <- q1           # F draws from q1's output

4. Symbol style

The style: option on the header line selects the symbol standard. It applies to every gate in the diagram.

logic "ALU slice" style: iec

5. Module blocks

Use module to group gates into a labeled sub-circuit box. Module blocks are useful for documenting hierarchical designs — each module renders as a named rectangle around its member gates.

logic "Hierarchical adder"
input A, B, Cin
output Sum, Cout

module "Half Adder" {
  s1 = XOR(A, B)
  c1 = AND(A, B)
}

Sum = XOR(s1, Cin)
Cout = OR(c1, AND(s1, Cin))

Module syntax rules:

• module "Label" { — opens a module (quoted label or bare identifier). The { must be on the same line.
• } on its own line closes the most recently opened module.
• Modules can be nested.

6. Labels & comments

• Diagram title: logic "Full Adder" — first line only.
• Gate signal names: the id in id = GATE(…) is both the gate name and the output wire name.
• Output labels: output Sum — the output port label matches the signal name by default.
• Active-low marker: ~ prefix on a port or gate input.
• Comments: # or -- at the start of a line, or after the last meaningful token on a line.

7. Reserved words & escaping

Reserved at line start: logic (header), input, output, module, }.

Reserved operator tokens — avoid these inside signal names: =, (, ), ,, <-, ~.

Signal name rules: must match [a-zA-Z_][a-zA-Z0-9_]*. Lowercase and uppercase are both accepted; gate type keywords (AND, OR, etc.) are case-insensitive in the parser.

8. Common mistakes

9. Grammar (EBNF)

document    = header statement*

header      = "logic" ( WS quoted-string )? ( WS "style:" WS style )? NEWLINE
style       = "ansi" | "iec"
quoted-string = '"' any-char-but-quote* '"'

statement   = blank | comment | input-decl | output-decl | gate-def | assign | module-block

comment     = ( "#" | "--" ) any NEWLINE

input-decl  = "input" WS port-list NEWLINE
output-decl = "output" WS port-list NEWLINE
port-list   = port-id ( "," WS? port-id )*
port-id     = "~"? id

gate-def    = id WS "=" WS gate-type "(" input-list ")" NEWLINE
input-list  = ( "~"? id ) ( "," WS? ( "~"? id ) )*

assign      = id WS "<-" WS id NEWLINE

module-block = module-open ( statement | module-block )* module-close
module-open  = "module" WS ( quoted-string | id ) WS? "{" NEWLINE
module-close = "}" NEWLINE

gate-type   = "AND" | "OR" | "NOT" | "NAND" | "NOR" | "XOR" | "XNOR" | "BUF"
            | "TRISTATE_BUF" | "TRISTATE_INV" | "OPEN_DRAIN" | "SCHMITT"
            | "DFF" | "JKFF" | "SRFF" | "TFF"
            | "LATCH_SR" | "LATCH_D"
            | "MUX" | "DEMUX" | "DECODER" | "ENCODER"
            | "COUNTER" | "SHIFT_REG"
            // all case-insensitive

id          = [a-zA-Z_] [a-zA-Z0-9_]*

Authoritative source: src/diagrams/logic/parser.ts. If this diverges from the parser, the parser wins — please open an issue.

10. Standard compliance

Schematex logic gate diagrams follow IEEE Std 91-1984 / ANSI Y32.14 (distinctive-shape symbols) and IEC 60617-12 (rectangular symbols with function qualifiers).

What is implemented today:

• ✅ All eight combinational gates: AND, OR, NOT, NAND, NOR, XOR, XNOR, BUF
• ✅ Special-output buffers: TRISTATE_BUF, TRISTATE_INV, OPEN_DRAIN, SCHMITT
• ✅ Four edge-triggered flip-flops: DFF, JKFF, SRFF, TFF
• ✅ Two latches: LATCH_SR, LATCH_D
• ✅ Combinational MSI: MUX, DEMUX, DECODER, ENCODER
• ✅ Sequential MSI: COUNTER, SHIFT_REG
• ✅ Active-low (~) notation on inputs and ports
• ✅ ANSI and IEC symbol styles, selectable per diagram
• ✅ Module grouping blocks
• ✅ Automatic DAG layout (topological sort, left-to-right signal flow)
• ⏳ Explicit fan-out wire routing (shared net with junction dot)
• ⏳ Multi-bit bus notation (/N slash annotation on wire)
• ⏳ Active-low clock inputs on flip-flops

References:

• IEEE Std 91-1984 / ANSI Y32.14: IEEE Standard Graphic Symbols for Logic Functions
• IEEE Std 91a-1991: Supplement to IEEE Std 91
• IEC 60617-12: Graphical symbols for diagrams — binary logic elements

11. Related examples

12. Roadmap

Planned — not yet parseable. Do not use these in generated DSL today; the parser will reject or ignore them.

• Explicit fan-out / junction dot — named wire shared by multiple gate inputs, rendered with a junction dot at the branch point.
• Multi-bit bus notation — bus N annotation on a wire to denote an N-bit signal group.
• Active-low clock — ~CLK in a flip-flop input list rendering a bubble on the clock triangle.
• Feedback arc — explicit wire from a gate output back to an earlier gate input, routed above the main signal path.
• Parameterized gate fan-in — AND(A, B, C, D) rendering a 4-input AND gate directly.

Track in the GitHub issues if you need any of these sooner.