1-bit full adder: truth table, equations, and a five-gate check

A 1-bit full adder adds three one-bit inputs—A, B, and carry-in Cin—and returns a one-bit Sum plus carry-out Cout. For every input row, let N = A + B + Cin as ordinary integer addition. Then Sum = N mod 2 and Cout = floor(N / 2). The equivalent Boolean equations are Sum = A XOR B XOR Cin and Cout = AB + Cin(A XOR B). Two XOR gates, two AND gates, and one OR gate implement those equations, and all eight possible input combinations satisfy the invariant 2 × Cout + Sum = A + B + Cin.

Scope and terminology first

This note models ideal, active-high, combinational Boolean logic. Each input is exactly 0 or 1; each gate changes state without delay; and no voltage level, fan-out, loading, hazard, or clock is modeled. A truth table proves the stated Boolean function for every discrete input combination. It does not prove that a physical or synthesized circuit meets timing, power, test, or safety requirements.

A half adder adds only A and B. A full adder also accepts the carry from the less-significant bit, so it has three inputs and two outputs. MIT's 6.004 design-project appendix describes that same full adder as a three-input, two-output combinational circuit and gives S = A XOR B XOR Cin together with the three-product carry form Cout = AB + A·Cin + B·Cin.

In the equations below, juxtaposition means Boolean AND, + means Boolean OR, and XOR is exclusive OR. In the arithmetic invariant, + and × are ordinary integer operations. Naming the algebra prevents a common error: Boolean 1 + 1 evaluates to 1 under OR, while binary arithmetic 1 + 1 produces the two-bit result 10.

Inputs, outputs, and assumptions

The largest input total is 1 + 1 + 1 = 3, whose two-bit binary representation is 11. Two output bits are therefore sufficient: Cout has place value 2 and Sum has place value 1.

Work one row through arithmetic and gates

Take A = 1, B = 0, and Cin = 1. Ordinary integer addition gives

N = A + B + Cin
  = 1 + 0 + 1
  = 2
  = 10₂.

Sum  = N mod 2      = 0
Cout = floor(N / 2) = 1.

Now trace the same row through the five-gate network:

s1   = A XOR B       = 1 XOR 0 = 1
Sum  = s1 XOR Cin    = 1 XOR 1 = 0
c1   = A AND B       = 1 AND 0 = 0
c2   = s1 AND Cin    = 1 AND 1 = 1
Cout = c1 OR c2      = 0 OR 1  = 1.

The arithmetic result 10₂ and the gate outputs (Cout, Sum) = (1, 0) agree. The invariant closes numerically: 2 × 1 + 0 = 1 + 0 + 1 = 2.

Exhaust all eight input combinations

Three independent binary inputs have 2³ = 8 combinations. MIT 6.111's Arithmetic Structures slides publish the same eight-row full-adder table and equations; the table below independently recomputes each row from N.

Sum is 1 exactly when an odd number of inputs is 1, which is the parity function A XOR B XOR Cin. Cout is 1 exactly when at least two inputs are 1, which is the three-input majority function. That majority can be written as AB + A·Cin + B·Cin.

The rendered network uses the equivalent generate/propagate form:

generate  G = AB
propagate P = A XOR B
Cout        = G + P·Cin.

If A = B = 1, G is already 1; if exactly one of A and B is 1, P passes Cin into the carry result. If both are 0, neither term can assert Cout. The exhaustive table confirms that this compact form and the three-product form agree on all eight rows.

Reproducible Schematex source

logic "1-bit Full Adder" style: ansi
input A, B, Cin
output Sum, Cout
s1 = XOR(A, B)
Sum = XOR(s1, Cin)
c1 = AND(A, B)
c2 = AND(s1, Cin)
Cout = OR(c1, c2)

Schematex 1.0.13 strictly parsed and rendered this source with no diagnostics on August 27, 2026. The SVG contains three input ports, two output ports, two XOR gates, two AND gates, one OR gate, and twelve directed wire segments. The current Schematex logic syntax reference documents the functional assignment grammar and selectable ANSI/IEC styles. The IEEE/ANSI 91a-1991 standard page is cited only for the graphic-symbol scope; the MIT sources establish the arithmetic and Boolean behavior.

Checks and invariants

1. Exhaustiveness: the table must contain exactly 2³ = 8 unique input rows.
2. Binary reconstruction: every row must satisfy 2 × Cout + Sum = A + B + Cin.
3. Parity: Sum = 1 only for input weights 1 and 3.
4. Majority: Cout = 1 only for input weights 2 and 3.
5. Symmetry: swapping A and B cannot change either output.
6. Zero and maximum: 000 must produce 00; 111 must produce 11.
7. Structure: the source must render two XOR, two AND, and one OR gate with no undeclared signal.
8. Independent methods: the integer calculation, truth table, and gate trace must agree.

A useful negative test is to change Sum = XOR(s1, Cin) to Sum = OR(s1, Cin). Rows 011 and 101 then incorrectly produce Sum = 1 instead of 0; the binary-reconstruction invariant fails immediately. Deleting c2 = AND(s1, Cin) similarly loses the propagated carry for those two rows.

Failure modes and review boundary

Common mistakes are copying a two-input half-adder table, using OR where XOR is required, reading (Sum, Cout) in the wrong bit order, treating Boolean OR as integer addition, checking only the easy 000 and 111 rows, or drawing a familiar gate topology without tracing its named signals. Equivalent equations can look different; compare their outputs or reduce them algebraically instead of judging by shape alone.

The ideal model omits propagation delay, rise and fall time, static and dynamic hazards, drive strength, fan-out, logic-voltage thresholds, power, metastability, clock-domain behavior, physical implementation, HDL sizing rules, synthesis transformations, test coverage, and signed-overflow logic. Chaining cells into a ripple-carry adder introduces a carry timing path that this one-cell truth table does not analyze.

Open the exact Schematex full-adder example, then run the two negative tests above and recheck all eight rows. For a wider adder, chain Cout into the next cell's Cin, keep the same per-cell invariant, and add a separate timing analysis for the carry path.