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SCHEMATEX / RESEARCH NOTEWorked analysis · Electronics and measurement

Loaded voltage divider: output voltage and measurement error

Calculate a 10 kΩ / 10 kΩ divider before and after a 10 kΩ load, then verify the 3.333 V result with KCL, a Thévenin equivalent, and a meter-loading check.

KEY RESULT3.333 V

loaded output, down from the ideal unloaded value of 5.000 V

FIGURE 01 / REPRODUCIBLE OUTPUTSVG · SCHEMATEX
Loaded voltage-divider schematic with a 10 V source, 10 kiloohm upper resistor, and parallel 10 kiloohm lower and load resistors connected at the Vout node
Rendered deterministically by Schematex 1.0.13 from the positional circuit source reproduced here; strict rendering returned no diagnostics, and the divider, KCL, and Thévenin calculations were independently recomputed.

A 10 V divider with R1 = 10 kΩ, R2 = 10 kΩ, and a 10 kΩ load does not produce 5 V. The load sits in parallel with R2, making the effective lower leg 5 kΩ; therefore the loaded output is 10 V × 5 kΩ / (10 kΩ + 5 kΩ) = 3.333 V. The load lowers the output by 1.667 V, or 33.33% of the unloaded 5 V baseline.

Ten volt source feeds R1 of 10 kiloohms; the Vout node then returns to ground through parallel 10 kiloohm resistors R2 and RL
R2 and RL share both endpoints, Vout and ground, so they are parallel even if a drawing tool places their symbols at different horizontal positions.

Scope and terminology first

This is an ideal steady-state DC calculation. An ideal 10 V source holds its terminal voltage, each resistor has exactly its marked resistance, and wires have zero resistance. The result teaches topology and arithmetic; it does not select a real resistor, probe, ADC input, or power supply.

A voltage divider has an upper resistance from the source to the output node and a lower resistance from the output node to the reference node. In the unloaded case, those are R1 and R2. A load is anything connected from the output to another node that draws current. Here RL connects from Vout to ground, exactly across R2, so the lower leg becomes R2 || RL.

The ideal unloaded relationship is Vout/Vs = R2/(R1 + R2). Analog Devices' November 2018 voltage-divider laboratory note gives the same ratio and makes its boundary explicit: the simple resistive expression assumes ideal resistors and negligible parasitic effects. That boundary matters whenever frequency, input capacitance, or fast edges enter the problem.

Inputs and assumptions

QuantityValueRole
Vs10.000 V DCideal source voltage
R110.000 kΩupper divider resistor
R210.000 kΩlower divider resistor
RL10.000 kΩresistive load across the output
Reference0 Videal ground node

All resistances are positive and expressed in the same unit. The output has no other current path. There is no tolerance, source resistance, leakage, bias current, capacitance, inductance, noise, or temperature dependence.

Establish the unloaded baseline

Remove RL first. Only R1 and R2 carry current, so their series resistance is

Runloaded = R1 + R2
          = 10 kΩ + 10 kΩ
          = 20 kΩ.

The current through both resistors is

Iunloaded = Vs / Runloaded
          = 10 V / 20 kΩ
          = 0.500 mA.

The output is the drop across R2:

Vout,unloaded = Iunloaded × R2
              = 0.500 mA × 10 kΩ
              = 5.000 V.

This 5 V value is a baseline, not a promise about the loaded circuit.

Reduce the loaded lower leg

With RL connected, R2 and RL share the same two nodes. Their parallel equivalent is

Rlower = R2 || RL
       = (R2 × RL) / (R2 + RL)
       = (10 kΩ × 10 kΩ) / (10 kΩ + 10 kΩ)
       = 5.000 kΩ.

Now apply the divider relationship to R1 and Rlower:

Vout,loaded = Vs × Rlower / (R1 + Rlower)
            = 10 V × 5 kΩ / (10 kΩ + 5 kΩ)
            = 10 V × 1/3
            = 3.333 V.

The absolute change is 5.000 V - 3.333 V = 1.667 V. Relative to the unloaded value, the loading error is

(3.333 V - 5.000 V) / 5.000 V × 100% = -33.33%.

Report the sign. Saying only “33.33% error” hides whether loading raised or lowered the output.

Cross-check with current conservation

The total resistance seen by the source is R1 + Rlower = 15 kΩ, so the current through R1 is

IR1 = 10 V / 15 kΩ = 0.6667 mA.

Each 10 kΩ lower branch sees 3.333 V:

IR2 = 3.333 V / 10 kΩ = 0.3333 mA
IRL = 3.333 V / 10 kΩ = 0.3333 mA.

Kirchhoff's current-law check at Vout closes within rounding:

IR1 = IR2 + IRL
0.6667 mA = 0.3333 mA + 0.3333 mA.

If the incoming current does not equal the two outgoing branch currents, the topology, units, or rounding is wrong.

Cross-check with a Thévenin equivalent

MIT OpenCourseWare's Circuit Abstractions presents Thévenin equivalence as a way to replace a linear circuit with a simpler equivalent before connecting it to a larger circuit. Viewed from Vout with RL removed, this divider has

Vth = 5.000 V
Rth = R1 || R2 = 10 kΩ || 10 kΩ = 5.000 kΩ.

Reconnect RL = 10 kΩ:

Vout = Vth × RL / (Rth + RL)
     = 5 V × 10 kΩ / (5 kΩ + 10 kΩ)
     = 3.333 V.

The direct reduction, KCL check, and Thévenin check agree.

What a 1 MΩ meter would read

A measuring instrument is also a load. Keysight's application note 5988-5021EN explains that attaching a probe draws current; at low frequency, the probe's resistive input and the circuit's source resistance form another voltage divider. Replace the heavy 10 kΩ load with an idealized 1 MΩ meter input:

Rlower = 10 kΩ || 1 MΩ = 9.90099 kΩ
Vmeter = 10 V × 9.90099 / (10 + 9.90099)
       = 4.97512 V
error  = (4.97512 - 5.00000) / 5.00000 × 100%
       = -0.4975%.

That is a DC resistance example only. The same Keysight note warns that probe capacitance and connection inductance become important as frequency and edge rate increase; this article's resistor-only result must not be reused as a bandwidth or transient-accuracy claim.

Reproducible Schematex source

circuit "Loaded 10 kΩ voltage divider"
V1: voltage_source up value="10V" label="V1"
wire right 80
R1: resistor right value="10k" label="R1"
wire right 35
net VOUT: dot
label "Vout" up
at: VOUT
R2: resistor down value="10k" label="R2"
wire down 30
ground
at: VOUT
wire right 80
RL: resistor down value="10k" label="RL"
wire down 30
ground
at: V1.start
wire down 30
ground

Schematex 1.0.13 strictly parsed and rendered this source with no diagnostics on August 26, 2026. The SVG contains one voltage source, three resistors, an explicit VOUT junction, and three ground returns. The current Schematex circuit syntax reference documents positional components, named-net anchors, explicit wire lengths, junction dots, labels, and ground symbols. That owned page establishes renderer behavior; Analog Devices, MIT, and Keysight establish the circuit and measurement principles.

Checks and invariants

  1. Topology: R2 and RL must share both endpoints. Sharing only Vout does not make them parallel.
  2. Unloaded limit: removing RL must restore 5.000 V.
  3. Short-circuit limit: as RL approaches 0 Ω, Vout must approach 0 V.
  4. Open-circuit limit: as RL approaches infinity, R2 || RL must approach R2.
  5. Current conservation: IR1 = IR2 + IRL at the output node.
  6. Unit discipline: V/kΩ = mA; do not mix ohms and kiloohms without conversion.
  7. Monotonicity: a smaller positive RL cannot raise this ideal divider's output.
  8. Independent method: direct reduction and Thévenin reduction must return the same voltage.

Failure modes and review boundary

Common errors are applying the unloaded formula after connecting a load, adding parallel resistances directly, treating a voltmeter as infinite impedance, hiding a percent-error sign, and using a DC equivalent for a high-frequency probe. Real output also depends on resistor tolerance and temperature coefficient, source output resistance and current limit, input leakage or bias current, wiring resistance, noise, and frequency-dependent impedance.

Paste the source into the Schematex playground, then run two deliberate perturbations. Remove RL and confirm the output calculation returns to 5.000 V; restore it and change its value to 1M to confirm the result approaches 4.975 V. If the diagram does not preserve the shared vout and ground nets, stop before trusting any arithmetic.

References

  1. Doug Mercer and Antoniu Miclaus, Analog Devices. ADALM1000 SMU Training Topic 11: Frequency Compensated Voltage Dividers. Analog Dialogue, Volume 52, November 2018 StudentZone laboratory note, 2018. https://www.analog.com/en/resources/analog-dialogue/studentzone/2019/07/25/14/50/studentzone-november-2018.html Accessed August 26, 2026.
  2. Leslie Kaelbling, Jacob White, Harold Abelson, Dennis Freeman, Tomás Lozano-Pérez, and Isaac Chuang, Massachusetts Institute of Technology. Circuit Abstractions. MIT OpenCourseWare 6.01SC, Spring 2011 course session, 2011. https://ocw.mit.edu/courses/6-01sc-introduction-to-electrical-engineering-and-computer-science-i-spring-2011/pages/unit-3-circuits/circuit-abstractions/ Accessed August 26, 2026.
  3. Keysight Technologies. Optimizing Oscilloscope Measurement Accuracy on High-Performance Systems with Keysight Active Probes. 5988-5021EN; formerly Application Note 1385, Published in the USA, August 1, 2014, 2014. https://prc.keysight.com/Content/PDF_Files/5988-5021EN.pdf Accessed August 26, 2026.
  4. Schematex Project. Circuit schematic syntax reference. Schematex 1.0.13 public documentation. https://schematex.js.org/docs/circuit Accessed August 26, 2026.

Cite this article

Lena Ortiz. “Loaded voltage divider: output voltage and measurement error.” Schematex Research. Version 2026-08-26. Updated August 26, 2026. https://schematex.js.org/research/loaded-voltage-divider-calculation